In the kernel module makefile obj-m variable exists. Consider the following:
CUR = $(shell uname -r)
DIR = /lib/modules/$(CUR)/build
PWD = $(shell pwd)
obj-m := m1.o m2.o
default:
$(MAKE) -C $(DIR) SUBDIRS=$(PWD) modules
In this Makefile, the default target contains a recipe which invokes kernel sub-make. The obj-m variable doesn't get exported to environment thus sub-make cannot use it. But if we delete the obj-m variable initialization, then this make doesn't compile m1 and m2 kernel modules. So, question is:
Why kernel sub-make depends on the non-exported obj-m variable in this case?
None of the make variables are exported to the environment.
SUBDIRS gets defined as a make variable.
The kernel makefile looks for the Makefile in SUBDIRS, reads it, and uses any obj-* defined therein.
(According to the documentation, you should use M instead of SUBDIRS.)