You seem to have some confusion between the prerequisites of a make rule and its recipe. The prerequisites go on the same line as the target name; the recipe goes on the next tab-indented line or lines. Thus, for example, this rule ...

all:
    check

... says that target 'all' has no prerequisites (so it is always considered out of date), and that the recipe for building it is to run a command check. What you appear actually to want is to build the target named 'check', which you can cause to happen by making 'check' a prerequisite of 'all':

all: check

More generally, you seem to be approaching the makefile as if it were a program with multiple entry points, but it is much better viewed as a set of rules that make can use to build things. Thus, it is conventional and desirable for rules that actually build a file to specify the built file as a target. Moreover, to use the full power of make, you should express the proper prerequisites for those and other rules. For example:

./file1: file1.c
    gcc -o file1 file1.c

./file2: file2.c
    gcc file2.c -lm -o file2

res: ./file1 ./file2
    ./file1 someArgs ./file2 someArgs

If you do that correctly then you don't need hacks such as removing and rebuilding the programs every time -- make will figure out whether they are out of date, and will rebuild them if and when it needs to do.

The first target all is trying to run a command called check (and so is the target default). I think you want the command make to behave the same as the command make check and to perform the actions of the target called check in the Makefile. In that case, add it as a dependency like this:

all: check

default: check

clean:
    rm -rf file1 file2

rst:
    gcc -o file1 file1.c && gcc file2.c -lm -o file2

res:
    ./file1 someArgs ./file2 someArgs

check:
    make clean
    make rst
    make res