I'm trying to write a piece of code that achieves a very high TLB miss rate (over 95%). I have come up with the following C code that could reach around 30% d-TLB misses.

I use 4096 bytes page size on an Intel x86_64 processor and Ubuntu 20.04 (kernel v5.4).

#include <stdio.h>
#include <stdlib.h>

#define MEMORY_SIZE (1024 * 1024 * 1024)
#define PAGE_SIZE 4096
#define PAGE_COUNT (MEMORY_SIZE / PAGE_SIZE)

typedef unsigned char byte;
typedef byte Page[PAGE_SIZE];

int main(int argc, char *argv[])
{

    register int loop = 3000;
    Page *pages = (Page *)malloc(PAGE_COUNT * sizeof(Page));
    while (loop-- > 0)
    {
        for (register int i = 0; i < PAGE_COUNT; ++i)
        {
            register int page_num = (i % 2) ? i : PAGE_COUNT - i;
            pages[page_num][0]++;
        }
    }
    free(pages);
    return 0;
}

To compile: $ gcc main.c -o main

To Run and measure using perf command: $ sudo perf stat -e dTLB-loads-misses,dTLB-loads ./main

And here is the output:

Performance counter stats for './main':

       521,160,735      dTLB-loads-misses         #   28.02% of all dTLB cache accesses
     1,860,126,043      dTLB-loads                                                  

      12.759230463 seconds time elapsed

      12.429918000 seconds user
       0.328050000 seconds sys

The output of the cpuid command containing my TLB information:

   cache and TLB information (2):
      0x63: data TLB: 2M/4M pages, 4-way, 32 entries
            data TLB: 1G pages, 4-way, 4 entries
      0x03: data TLB: 4K pages, 4-way, 64 entries
      0x76: instruction TLB: 2M/4M pages, fully, 8 entries
      0xb5: instruction TLB: 4K, 8-way, 64 entries
      0xc3: L2 TLB: 4K/2M pages, 6-way, 1536 entries

The question is, how to achieve much higher TLB misses (over 95%)?

Thanks